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1 ? fn6602.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners. ISL6622B vr11.1 compatible synchronous rectified buck mosfet drivers the ISL6622B is a high frequen cy mosfet driver designed to drive upper and lower power n-channel mosfets in a synchronous rectified buck converter topology. the advanced pwm protocol of ISL6622B is s pecifically designed to work with intersil vr11.1 controllers and combined with n-channel mosfets, form a complete core-voltage regulator solution for advanced microprocessors. when ISL6622B detects a psi pwm protocol sent by an intersil vr11.1 controller, it activates diode emulation (de) operation; otherwise, it operates in normal continuous conduction mode (ccm) pwm mode. in the 8 ld soic package, the ISL6622B drives the upper gate to 12v while the lower driv e voltage is fixed at 5.75v. the 10 ld dfn part offers more flexibility: the upper gate can be driven from 5v to 12v via the uvcc pin, while the lower gate has a resistor-selectable drive voltage of 5.75v, 6.75v, and 7.75v (typically). this provides the flexibility necessary to optimize applications involving trade-offs between gate charge and conduction losses. to further enhance light load efficiency, the ISL6622B enables diode emulation operation during psi mode. this allows for discontinuous conduction mode (dcm) operation by detecting when the inductor current reaches zero and subsequently turning off the low side mosfet to prevent it from sinking current. an advanced adaptive shoot-throug h protection is integrated to prevent both the upper and lower mosfets from conducting simultaneously and to minimize dead time. the ISL6622B has a 20k integrated high-side mosfet gate-to-source resistor to prev ent self turn-on due to high input bus dv/dt. this driver also has an overvoltage protection feature operational while vcc is below the por threshold: the phase n ode is connected to the gate of the low side mosfet (lgate) via a 10k resistor, limiting the output voltage of the converter cl ose to the gate threshold of the low side mosfet, dependent on the current being shunted, which provides some protection to the load should the upper mosfet(s) be shorted prior to start-up. features ? dual mosfet drives for sy nchronous rectified bridge ? advanced adaptive zero shoot-through protection ? integrated ldo with selectable lower gate drive voltage for light load efficiency optimization ? 36v internal bootstrap diode ? advanced pwm protocol (patent pending) to support psi operation ? diode emulation for enhanced light load efficiency ? bootstrap capacitor ov ercharging prevention ? supports high switching frequency - 3a sinking current capability - fast rise/fall times and low propagation delays ? integrated ugate-to-phase resistor for increased upper mosfet input bus high dv/dt immunity ? pre-por overvoltage protection at start-up and shutdown ? dual flat no-lead (dfn) package - near chip-scale package footprint; improves pcb efficiency and thinner in profile - bottom copper pad for enhanced heat sinking ? pb-free (rohs compliant) applications ? high light-load efficiency voltage regulators ? core regulators for advanced microprocessors ? high current dc/dc converters ? high frequency and high efficiency vrm and vrd related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensit ive surface mount devices (smds)? ? technical brief tb417 ?designing stable compensation networks for single phase voltage mode buck regulators? for power train design, layout guidelines, and feedback compensation design data sheet march 19, 2009
2 march 19, 2009 ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL6622Bcbz* 6622b cbz 0 to +70 8 ld soic m8.15 ISL6622Bcrz* 622b 0 to +70 10 ld 3x3 dfn l10.3x3 ISL6622Bibz* 6622b ibz -40 to +85 8 ld soic m8.15 ISL6622Birz* 22bi -40 to +85 10 ld 3x3 dfn l10.3x3 *add ?-t? suffix for tape and reel. please refer to tb347 for details on reel specifications. note: these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materi als, and 100% matte tin plate plus anneal (e3 term ination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. pinouts ISL6622B (8 ld soic) top view ISL6622B (10 ld 3x3 dfn) top view ugate boot pwm gnd 1 2 3 4 8 7 6 5 phase vcc lvcc lgate ugate boot gd_sel pwm phase vcc uvcc lvcc gnd lgate 2 3 4 1 5 9 8 7 10 6 pad block diagrams ISL6622B uvcc = vcc for soic lvcc = 5.75v (typically) at 50ma for soic lvcc vcc pwm +5v 11.2k 9.6k boot ugate phase lgate gnd shoot- through protection uvcc 20k 10k gd_sel ldo lvcc control logic por/ ISL6622B
3 march 19, 2009 typical application circuit ref dac vcc comp fb imon vdiff vsen rgnd en_vtt vtt vr_rdy vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 psi +5v tm tcomp ofs fs ss gnd p load vin +5v en_pwr isl6334 +5v isen1- isen1+ pwm1 isen2- isen2+ pwm2 isen3- isen3+ pwm3 isen4- isen4+ pwm4 vr_fan vr_hot ntc +12v vcc lvcc pwm boot ugate phase lgate gnd vin +12v vcc pvcc pwm boot ugate phase lgate gnd vin +12v vcc pvcc pwm boot ugate phase lgate gnd vin +12v vcc pvcc pwm boot ugate phase lgate gnd vin isl6612 driver isl6612 driver isl6612 driver ISL6622B driver isl6334 ISL6622B
4 march 19, 2009 z absolute maximum rati ngs thermal information supply voltage (vcc, uvcc) . . . . . . . . . . . . . . . . . . . . . . . . . . .15v boot voltage (v boot-gnd ). . . . . . . . . . . . . . . . . . . . . . . . . . . .36v input voltage (v pwm ) . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 7v ugate. . . . . . . . . . . . . . . . . . . v phase - 0.3v dc to v boot + 0.3v v phase - 3.5v (<100ns pulse width, 2j) to v boot + 0.3v lgate . . . . . . . . . . . . . . . . . . gnd - 0.3v dc to v lvcclvcc + 0.3v gnd - 5v (<100ns pulse width, 2j) to v lvcclvcc + 0.3v phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v dc to 15v dc gnd - 8v (<400ns, 20j) to 30v (<200ns, v boot-gnd <36v) thermal resistance ja (c/w) jc (c/w) soic package (note 1) . . . . . . . . . . . . 100 n/a dfn package (notes 2, 3) . . . . . . . . . . 48 7 maximum junction temperature (plastic package) . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions ambient temperature range ISL6622Bibz, ISL6622Birz . . . . . . . . . . . . . . . . .-40c to +85c ISL6622Bcbz, ISL6622Bcrz . . . . . . . . . . . . . . . . . 0c to +70c maximum operating junction temperature. . . . . . . . . . . . . +125c supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8v to 13.2v supply voltage range, uvcc . . . . . . . . . . . . . . . . . . 4.75v to 13.2v caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 2. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 3. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 4. limits should be considered typi cal and are not production tested. electrical specifications recommended operating conditions. parameters with mi n and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits es tablished by characterization and are not production tested. parameter symbol test conditions min typ max units vcc supply current no load switching supply current i vcc ISL6622Bcbz and ISL6622Bibz, f pwm = 300khz, v vcc = 12v -8.6-ma i vcc ISL6622Bcrz and ISL6622Birz, f pwm = 300khz, v vcc = 12v -6.6-ma i uvcc -2-ma standby supply current i vcc ISL6622Bcbz and ISL6622Bibz, pwm transition from 0v to 2.5v -5.1-ma i vcc ISL6622Bcrz and ISL6622Birz, pwm transition from 0v to 2.5v -5.0-ma i uvcc -0.07- ma power-on reset vcc rising threshold 6.25 6.45 6.70 v vcc falling threshold 4.8 5.0 5.25 v lvcc rising threshold (note 4) -4.4- v lvcc falling threshold (note 4) -3.4- v pwm input (see ?timing diagram? on page 6) input current i pwm v pwm = 5v - 500 - a v pwm = 0v - -430 - a pwm rising threshold vcc = 12v - 3.4 - v pwm falling threshold vcc = 12v - 1.6 - v tristate lower gate falling threshold vcc = 12v - 1.60 - v tristate lower gate rising threshold vcc = 12v - 1.1 - v tristate upper gate rising threshold vcc = 12v - 3.2 - v tristate upper gate falling threshold vcc = 12v - 2.8 - v ISL6622B
5 march 19, 2009 ugate rise time t ru v vcc = 12v, 3nf load, 10% to 90% - 26 - ns lgate rise time t rl v vcc = 12v, 3nf load, 10% to 90% - 18 - ns ugate fall time t fu v vcc = 12v, 3nf load, 90% to 10% - 18 - ns lgate fall time t fl v vcc = 12v, 3nf load, 90% to 10% - 12 - ns ugate turn-on propagation delay (note 4) t pdhu v vcc = 12v, 3nf load, adaptive - 20 - ns lgate turn-on propagation delay (note 4) t pdhl v vcc = 12v, 3nf load, adaptive - 10 - ns ugate turn-off propagation delay (note 4) t pdlu v vcc = 12v, 3nf load - 10 - ns lgate turn-off propagation delay (note 4) t pdll v vcc = 12v, 3nf load - 10 - ns tristate low delay t tsld v vcc = 12v - 60 - ns minimum lgate on-time during psi operation t lg_on_dm v vcc = 12v 230 330 450 ns output (note 4) upper drive source current i u_source v vcc = 12v, 3nf load - 1.25 - a upper drive source impedance r u_source 20ma source current - 2.0 - upper drive sink current i u_sink v vcc = 12v, 3nf load - 2 - a upper drive sink impedance r u_sink 20ma sink current - 1.35 - lower drive source current i l_source v vcc = 12v, 3nf load - 2 - a lower drive source impedance r l_source 20ma source current - 1.35 - lower drive sink current i l_sink v vcc = 12v, 3nf load - 3 - a lower drive sink impedance r l_sink 20ma sink current - 0.90 - electrical specifications recommended operating conditions. parameters with mi n and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits es tablished by characterization and are not production tested. (continued) parameter symbol test conditions min typ max units functional pin description package pin # pin symbol function soic dfn 1 1 ugate upper gate drive output. connect to gate of high-side power n-channel mosfet. 2 2 boot floating bootstrap supply pin for the upper gate driv e. connect the bootstrap capacitor between this pin and the phase pin. the bootstrap capacitor provides the charge to turn on the upper mosfet. see ?internal bootstrap device? on page 7 for guidance in choosing the capacitor value. - 3 gd_sel this pin sets the lg drive voltage. 3 4 pwm the pwm signal is the control input for the driver. the pw m signal can enter three distin ct states during operation, see ?advanced pwm protocol (patent pending)? on page 6 for further details. connect this pin to the pwm output of the controller. 4 5 gnd bias and reference ground. all signals are referenced to this node. it is also the power ground return of the driver. 5 6 lgate lower gate drive output. connect to gate of the low-side power n-channel mosfet. 6 7 lvcc this pin provides power for the lg ate drive. place a high quality low esr ce ramic capacitor from this pin to gnd. - 8 uvcc this pin supplies power to the upper gate drive. its operating range is +5v to +12v. place a high quality low esr ceramic capacitor from this pin to gnd. 7 9 vcc connect this pin to 12v bias supply . this pin supplies power to the upper gate in the soic and to the ldo for the lower gate drive. place a high quality low esr ceramic capacitor from this pin to gnd. 8 10 phase connect this pin to the source of the upper mosfet and the drain of the lower mosfet. this pin provides a return path for the upper gate drive. - 11 pad connect this pad to the power ground plane (gnd) via thermally enhanced connection. ISL6622B
6 march 19, 2009 description operation and adaptive shoot-through protection designed for high speed switching, the ISL6622B mosfet driver controls both high-si de and low-side n-channel fets from one externally provided pwm signal. a rising transition on pwm initia tes the turn-off of the lower mosfet (see figure 1). afte r a short propagation delay [t pdll ], the lower gate begins to fall. typical fall time [t fl ] is provided in the ?electrical specifications? on page 5. following a 25ns blanking period, adapti ve shoot-through circuitry monitors the lgate voltage and turns on the upper gate following a short delay time [t pdhu ] after the lgate voltage drops below ~1.75v. the upper gate drive then begins to rise [t ru ] and the upper mosfet turns on. a falling transition on pwm indicates the turn-off of the upper mosfet and the turn-on of the lower mosfet. a short propagation delay [t pdlu ] is encountered before the upper gate begins to fall [t fu ]. the adaptive shoot-through circuitry monitors the ugate-phase voltage and turns on the lower mosfet a short delay time [t pdhl ] after the upper mosfet?s phase voltage drops below +0.8v or 40ns after the upper mosfet?s gate volt age [ugate-phase] drops below ~1.75v. the lower gate then rises [t rl ], turning on the lower mosfet. these methods prevent both the lower and upper mosfets from conducting simultaneously (shoot-through), while adapting the dead time to the gate charge characteristics of the mosfets being used. this driver is optimized for vo ltage regulators with large step down ratio. the lower mosfet is usually sized larger compared to the upper mosfet because the lower mosfet conducts for a longer time during a switching period. the lower gate driver is therefore si zed much larger to meet this application requirement. the 0.8 on-resistance and 3a sink current capability enable the lower gate driver to absorb the current injected into the lower gate through the drain-to-gate capacitor of the lower mosfet and help prevent shoot-through caused by the se lf turn-on of the lower mosfet due to high dv/dt of the switching node. advanced pwm protocol (patent pending) the advanced pwm protocol of ISL6622B is specifically designed to work with intersil vr11.1 controllers. when ISL6622B detects a psi protocol sent by an intersil vr11.1 controller, it turns on diode emul ation operation; otherwise, it remains in norma l ccm pwm mode. another unique feature of isl 6622b and other intersil drivers is the addition of a tristate shutdown window to the pwm input. if the pwm signal enters and remains within the shutdown window for a set holdoff time, the driver outputs are disabled and both mosfet gates are pulled and held low. the shutdown state is removed when the pwm signal moves outside the shutdown window. otherwise, the pwm rising and falling thresholds outlined in the ?electrical specifications? on page 4 determine when the lower and upper gates are enabled. this feature helps prevent a negative transient on the output voltage when the output is shut down, eliminating the schottky diode that is used in some systems for protecting the load from reversed output voltage events. note that for a pwm low to tr i-level (2.5v) transition, the lgate will not turn off until the diode emulation minimum on-time of 350ns is expired. diode emulation diode emulation allows for higher converter efficiency under light-load situations. with diode emulation active, the ISL6622B detects the zero curr ent crossing of the output inductor and turns off lgate. this prevents the low side mosfet from sinking current and ensures that discontinuous conduction mode (dcm) is achieved. the lgate has a minimum on-time of 350ns in dcm mode. gate voltage optimization technology (gvot) the ISL6622B provides the user flexibility in choosing the gate drive voltage for efficiency optimization. in applications when the switching losses dominate system performance, dropping pwm ugate lgate t fl t pdhu t pdll t rl t tshd t pdts t pdts 1.5vISL6622B
7 march 19, 2009 down to a lower drive voltage with gvot can improve the switching losses seen and maximize system efficiency. figure 2 shows that the gate drive voltage optimization is accomplished via an internal low drop out regulator (ldo) that regulates the lower gate drive voltage. lvcc is driven to a lower voltage depending on the gd_sel pin impedance. the input and output of this internal regulator are the vcc and lvcc pins, respectively. both vcc and lvcc should be decoupled with a high quality, low esr ceramic capacitor. in the 8 ld soic package, the ISL6622B drives the upper gate to 12v while the lower driv e voltage is fixed at 5.75v. the 10 ld dfn part offers more flexibility: the upper gate can be driven from 5v to 12v via the uvcc pin, while the lower gate has a resistor-selectable drive voltage of 5.75v, 6.75v, and 7.75v (typically). this provides the flexibility necessary to optimize applications involving trade-offs between gate charge and conduction losses. table 1 shows the ldo output (lvcc) level set by gd_sel pin impedance. figure 3 illustrates the internal ldo?s variation with the average load current plotted ov er a range of temperatures spanning from -40 c to +120 c. should finer tweaking of this lvcc voltage be necessary, a resistor (r cc ) can be used to shunt the ldo, as shown in figure 2. the resistor thus delivers part of the lgate drive current, leaving less current going through the internal ldo, elevating the ldo?s output voltage. further reduction in rcc?s value can raise the lvcc voltage further, as desired. power-on reset (por) function during initial start-up, the vcc voltage rise is monitored. once the rising vcc voltage exceeds the rising por threshold, operation of the driver is enabled and the pwm input signal takes control of the gate drives. if vcc drops below the por falling threshold, operation of the driver is disabled. pre-por overvoltage protection while vcc is below its por level, the upper gate is held low and lgate is connected to th e phase pin via an internal 10k (typically) resistor. by connecting the phase node to the gate of the low side mosfet, the driver offers some passive protection to the load if the upper mosfet(s) is or becomes shorted. if the phase node goes higher than the gate threshold of the lower mosfet, it results in the progressive turn-on of the device and the ef fective clamping of the phase node?s rise. the actu al phase node clam ping level depends on the lower mosfet?s electrical characteristics, as well as the characteristics of the input suppl y and the path connecting it to the respective phase node. internal bootstrap device the ISL6622B features an inte rnal bootstrap schottky diode. simply adding an external capacitor across the boot and phase pins completes the boots trap circuit. the bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to th e large negative swing at the trailing-edge of the phase node. this reduces the voltage stress on the boot to phase pins. the bootstrap capacitor must have a maximum voltage rating well above the maximum voltage intended for uvcc. its minimum capacitance value can be estimated from equation 1: where q g1 is the amount of gate charge per upper mosfet at v gs1 gate-source voltage and n q1 is the number of control mosfets. the v boot_cap term is defined as the allowable droop in the rail of the upper gate drive. select results are exemplified in figure 4. table 1. ldo operation and options pwm input gd_sel pin lvcc @ 50ma dc load don?t care floating 5.75v (typical; fixed in soic package) 4.5k to gnd 6.75v(typical) gnd 7.75v(typical) figure 2. gate voltage optimization (gvot) detail external circuit ISL6622B internal circuit vin vcc lvcc 1f 1f set by gd_sel gvot ldo rcc = option for higher lvcc rcc than pre-set by gd_sel + - + - > lgate driver 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 0 20406080100 average load current (ma) lvcc voltage (v) figure 3. typical lvcc variation with load gd_sel tied to gnd gd_sel tied to 4.5k to gnd gd_sel floating +120c +40c -40c c boot_cap q gate v boot_cap -------------------------------------- q gate q g1 uvcc ? v gs1 ----------------------------------- - n q1 ? = (eq. 1) ISL6622B
8 march 19, 2009 power dissipation package power dissipation is mainly a function of the switching frequency (f sw ), the output drive impedance, the layout resistance, and the selected mosfet?s internal gate resistance and total gate charge (q g ). calculating the power dissipation in the driver for a desired application is critical to ensure safe operation. exceeding the maximum allowable power dissipation level may push the ic beyond the maximum recommended operating junction temperature. the dfn package is more suitable for high frequency applications. see ? layout considerations ? on page 8 for thermal impedance improvement suggestions. the to tal gate drive power losses due to the gate charge of mosfets and the driver?s internal circuitry and their corresponding average driver current can be estimated with equations 2 and 3, respectively: where the gate charge (q g1 and q g2 ) is defined at a particular gate to source voltage (v gs1 and v gs2 ) in the corresponding mosfet data sheet; i q is the driver?s total quiescent current with no l oad at both drive outputs; n q1 and n q2 are number of upper and lower mosfets, respectively; uvcc and lvcc are the drive voltages for both upper and lower fets, respectively. the i q* vcc product is the quiescent power of the driver without a load. the total gate drive power loss es are dissipated among the resistive components along the transition path, as outlined in equation 4. the drive resistance dissipates a portion of the total gate drive power losses, t he rest will be dissipated by the external gate resistors (r g1 and r g2 ) and the internal gate resistors (r gi1 and r gi2 ) of mosfets. figures 5 and 6 show the typical upper and lower gate drives turn-on current paths. application information layout considerations during switching of the devices, the parasitic inductances of the pcb and the power devices? packaging (both upper and lower mosfets) leads to ringing, possibly in excess of the absolute maximum rating of the devices. carefu l layout can help minimize such unwanted st ress. the following advice is meant to lead to an optimized layout: ? keep decoupling loops (l vcc-gnd and boot-phase) as short as possible. ? minimize trace inductance, es pecially low-impedance lines: all power traces (ugate, phase, lgate, gnd, lvcc) should be short and wide, as much as possible. 50nc 20nc figure 4. bootstrap capacitance vs boot ripple voltage v boot_cap (v) c boot_cap (f) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 q gate = 100nc p qg_tot p qg_q1 p qg_q2 i q vcc ? ++ = (eq. 2) p qg_q1 q g1 uvcc 2 ? v gs1 --------------------------------------- f sw ? n q1 ? = p qg_q2 q g2 lvcc 2 ? v gs2 -------------------------------------- f sw ? n q2 ? = i dr q g1 uvcc n q1 ? ? v gs1 ----------------------------------------------------- - q g2 lvcc n q2 ? ? v gs2 ---------------------------------------------------- - + ?? ?? ?? f sw i q + ? = (eq. 3) figure 5. typical upper-gate drive turn-on path figure 6. typical lower-gate drive turn-on path p dr p dr_up p dr_low i q vcc ? ++ = (eq. 4) p dr_up r hi1 r hi1 r ext1 + -------------------------------------- r lo1 r lo1 r ext1 + ---------------------------------------- + ?? ?? ?? p qg_q1 2 --------------------- ? = p dr_low r hi2 r hi2 r ext2 + -------------------------------------- r lo2 r lo2 r ext2 + ---------------------------------------- + ?? ?? ?? p qg_q2 2 --------------------- ? = r ext1 r g1 r gi1 n q1 ------------- + = r ext2 r g2 r gi2 n q2 ------------- + = q1 d s g r g1 r l1 boot r hi1 c ds c gs c gd r lo1 phase uvcc lvcc q2 d s g r g2 r l2 r hi2 c ds c gs c gd r lo2 ISL6622B
9 march 19, 2009 ? minimize the inductance of the phase node: ideally, the source of the upper and the drain of the lower mosfet should be as close as thermally allowable. ? minimize the input current loop: connect the source of the lower mosfet to ground as close to the transistor pin as feasible; input capacitors (especially ceramic decoupling) should be placed as close to the drain of upper and source of lower mosfets as possible. in addition, for improved heat dissipation, place copper underneath the ic whether it has an exposed pad or not. the copper area can be extended be yond the bottom area of the ic and/or connected to bur ied power ground plane(s) with thermal vias. this combination of vias for vertical heat escape, extended surface copper islands, and buried planes combine to allow the ic and the power switches to achieve their full thermal potential. upper mosfet self turn -on effect at start-up should the driver have insufficient bias voltage applied, its outputs are floating. if the input bus is energized at a high dv/dt rate while the driver outputs are floating, due to self coupling via the internal c gd of the mosfet, the gate of the upper mosfet could momentarily rise up to a level greater than the threshold voltage of th e device, potentially turning on the upper switch. therefore, if such a situation could conceivably be encountered, it is a common practice to place a resistor (r ugph ) across the gate and source of the upper mosfet to suppress the miller coupling effect. the value of the resistor depends mainly on the input voltage?s rate of rise, the c gd /c gs ratio, as well as the gate-source threshold of the upper mosfet. a higher dv/dt, a lower c ds /c gs ratio, and a lower gate-source threshold upper fet will require a smaller resistor to diminish the effect of the internal capacitive coupling. for most applications, the integrated 20k resistor is sufficient, not affecting normal performance and efficiency. the coupling effect can be roughly estimated with equation 5, which assumes a fixed linear input ramp and neglects the clamping effect of the body diode of the upper drive and the bootstrap capacitor. other parasitic components, such as lead inductances and pcb capacitances, are also not taken into account. figure 7 provides a visual reference for this phenomenon and its potential solution. gate drive voltage options intersil provides various gate drive voltage options in the isl6622 product family, as shown in table 2. the isl6622 can drop the low-side mosfet?s gate drive voltage when operating in dem, while the high-side fet?s gate drive voltage of the dfn package can be connected to vcc or lvcc. the isl6622a allows the low- side mosfet(s) to operate from an externally-provided rail as low as 5v, eliminating the ldo losses, while the high-sid e mosfet?s gate drive voltage of the dfn package can be connected to vcc or lvcc. the ISL6622B sets the low-side mosfet?s gate drive voltage at a fixed, programmable ldo le vel, while the highside fets? gate drive voltage of the dfn package can be connected to vcc or lvcc. v gs_miller dv dt ------- rc rss 1e v ? ds dv dt ------- rc ? iss ? --------------------------------- - ? ?? ?? ?? ?? ?? ?? ?? = rr ugph r gi + = c rss c gd = c iss c gd c gs + = (eq. 5) figure 7. gate to source resistor to reduce upper mosfet miller coupling vin q upper d s g r g r ugph boot c ds c gs c gd phase uvcc ISL6622B c boot ugate > 20k v gs_miller dv dt ------- rc rss 1e v ? ds dv dt ------- rc ? iss ? --------------------------------- - ? ?? ?? ?? ?? ?? ?? ?? = rr ugph r gi + = c rss c gd = c iss c gd c gs + = (eq. 6) table 2. isl6622 family options power rails lvcc uvcc vcc psi = low psi = high isl6622 soic 5.75v 11.2v vcc operating voltage ranges from 6.8v to 13.2v dfn programmable 11.2v separate rail isl6622a soic separate rail vcc dfn separate rail separate rail ISL6622B soic 5.75v vcc dfn programmable separate rail ISL6622B
10 march 19, 2009 ISL6622B dual flat no-lead plastic package (dfn) d e a b 0.10 mc e 0.415 c section "c-c" nx (b) (a1) 2x c 0.15 0.15 2x b nx l ref. (nd-1)xe 5 a c (datum b) d2 d2/2 e2 e2/2 top view 7 bottom view 5 6 index area 8 ab nx k 6 index area (datum a) 12 n-1 n nx b 8 nx b nx l 0.200 c a seating plane 0.08 c a3 side view 0.10 c l10.3x3 10 lead dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a3 0.20 ref - b 0.18 0.23 0.28 5,8 d 3.00 bsc - d2 1.95 2.00 2.05 7,8 e 3.00 bsc - e2 1.55 1.60 1.65 7,8 e 0.50 bsc - k0.25 - - - l0.30 0.35 0.40 8 n102 nd 5 3 rev. 3 6/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389. for odd terminal/side c l e terminal tip l c c
11 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com march 19, 2009 ISL6622B small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 8 0 8 - rev. 1 6/05

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